FIG. 1 shows a prior art of demapping and clock-recovery apparatus for Optical Channel Data Unit (ODU1) having a VC-4-17C frame structure.
In FIG. 1, a read-control module generates a gapped clock CLKb according to a mapping structure, as well as a clock and actual data, and writes the actual ODU1 data into a First-In First-Out Memory (FIFO) 1, according to the clock CLKb. A smooth-control module generates a smooth gapped clock CLKa according to the mapping structure and the actual data, in which case the clock CLKa includes uniformly-distributed gaps. The clock CLKa is used for controlling the reading speed of the FIFO 1, and data read from the FIFO 1 is stored in a FIFO 2. An ODU1-clock generating module generates a clock for the actual data ODU1, i.e. an ODU1 clock, by smoothing the clock CLKa with uniformly-distributed gaps through a phase-lock loop. The ODU1 clock controls the reading speed of the FIFO 2.
The above demapping and clock recovery apparatus makes it possible to recover an ODU1 clock with low jitter from VC-4-17C frames, and to ensure the high performance of the clock and the data.
In an Optical Transmit Network (OTN), OTN signals of low rate level may be asynchronously mapped and multiplexed into an OTN signal of high rate level; the OTN signals of low rate level represent low-order OTN frames, and the OTN signal of high rate level represents high-order OTN frames. There has been proposed a method of asynchronously mapping ODUj signals into an ODTUjk (ODTU: Optical channel Data Tributary Unit) signal, and a method of multiplexing ODTUjk signals into an OPUk (OPU: Optical Channel Payload Unit).
The method of asynchronously mapping ODUj signals into an ODTUjk signal will be illustrated briefly in conjunction with FIG. 2 and FIG. 3, in an example where 4 ODU0 signals are asynchronously mapped and multiplexed into an OTU5G (OTU: Optical Channel Transmit Unit).
For the ODU0 signals belonging to different clock domains, initially, justification bytes are generated through rate adaptation, to form ODTU0x frames as shown in FIG. 2. The ODTU0x frame shown in FIG. 2 has the following structure: 952 columns×16 (4×4) rows, and one column of Justification Overhead (JOH), where columns no. 473-476 of the ODTU0x frame are fixedly stuffed columns, and the ODTU0x includes a justified ODU0 frame, a positive justification location of 2 bytes and a negative justification location of 1 byte. In FIG. 2, NJO in the JOH is the negative justification byte, and PJO1 and PJO2 located in the same row as the NJO are the two positive justification bytes.
After the ODTU0x frames are formed, the four ODTU0x frames are multiplexed into an OPU5G signal through byte interleaving, and finally the OTU5G signal is formed to be transmitted and managed in the network.
The actual mapping structure for mapping four ODU0 signals into an OPU5G signal is shown in FIG. 3.
When OTN frames of low rate level, such as ODUj signals, are recovered from high rate OTN frames such as OTU5G and OTUk, for example, when an ODU0 signal is demapped and recovered from an ODTU0x signal, an asynchronous clock of the ODU0 signal is recovered from OTU5G. Because, different from the fixed stuffing and asynchronous rate justification control in units of bit for recovering ODU1 from VC-4-17C, stuffing and asynchronous justification of the high rate OTN frame is performed in units of byte, a great deal of mapping and combining jitters are certainly generated during the asynchronously mapping and demapping process. However, the OTN service has strict requirements on jitter. Therefore, when OTN frames of low rate level are recovered from high rate OTN frames by using the existing clock recovery method, it is difficult to guarantee the clock jitter performance of the actually output ODUx, and it is also difficult to satisfy the requirements of the OTN service on jitter.